There are two major types of low level protocols used for data communications: asynchronous and synchronous. Asynchronous communications synchronizes on the byte level: each byte transmitted has one or more start and stop bits. The asynchronous protocol is useful at slower speeds, but there is a performance penalty in using start and stop bits for each byte transmitted. Higher speed transmissions generally use synchronous or block oriented communication protocols. Known synchronous protocols require that transmissions be synchronized at the block level instead of at the byte level. As blocks may be thousands of bytes long, the overhead of synchronization bits or bytes in synchronous transmissions is overcome by the overhead of start and stop bits in asynchronous transmissions.
Synchronous data communications initially used "sync" bytes at the beginning of a message to synchronize modems. At least a couple of valid sync bytes would have to be received correctly before the line was considered to be in "sync". A data block would then be delimited by start of text and end of text bytes. "Sync" would then have to be reacquired for the next block received.
The technique of using sync bytes was followed by the use of "bit stuffing" protocols like HDLC and SDLC where a sync flag (Hex "6E" or Binary "01111110") was reserved for synchronization. These protocols got their ("bit stuffing") name because every time that five "one" data bits were transmitted, a single "zero" bit was inserted in the output stream. The sync flag was also used to separate data blocks. The quality of data communications facilities had advanced by this time so that it was no longer necessary to actually resynchronize each block--rather a data block could follow another data block separated by a single sync flag.
A recent addition to the synchronous data communication protocols is Asynchronous Transfer Mode (ATM). It is a layered protocol operating at approximately 45 Mhz. The ATM DS3 Transmission System Sublayer (TSS) contains line synchronization. An ATM DS3 TSS frame consists of 4760 consecutive sequential bits, with 56 overhead bits intermixed in 4704 payload bits. Half of the overhead bits are framing bits, used for synchronization. Thus, there is a framing bit every 170 bits in the sequential input stream. Note that a 4760 bit block follows another 4760 bit block--without anything intervening in the sequential input stream.
Frame lock or synchronization is often a two step process when receiving ATM TSS frames. First the frame bits within a sequential input data stream are identified. A repeating sequence of "1001" (Binary) must be found in the framing bits. The framing bit location is usually confirmed by requiring that the "1001" sequence be found repeated a certain number of times in the sequential input stream, since such a sequence could occur naturally in the payload portion of a frame. As there are 28 framing bits within an ATM TSS block, there can be seven different possible block starting points once a repeating "1001" sequence is identified in the framing bits. So, the second step is to determine which one of the seven possible starting points is correct. This second step is done by looking at some of the other 28 overhead bits in a sequential input stream.
One method of identifying framing bits within an ATM sequential input data stream has been to test a bit from the sequential input stream. If that bit is possibly a framing bit, 169 bits from the sequential input stream are skipped, and the 171st bit is checked. If this bit is possibly a framing bit, another 169 bits are skipped, and the 341st bit is checked. This search is repeated until either a bit fails the framing bit test, or a sufficient number of bits have been tested to assure that the sequence detected indeed contains framing bits. Otherwise, the cycle is restarted. Note that it may be necessary to restart the cycle upwards of 680 times before successfully identifying the framing bits in a sequential input stream. The major disadvantage of this method is that it can take quite a long time to identify the framing bits in a sequential input stream.
One improvement to the above method has been to store upwards of a 4760 bit block in RAM. Then a search is made of the bits stored. For example, the first bit in storage is tested. If it is a one ("1") bit, 169 bits are skipped, and the 171st bit is tested. If the 171st bit is a zero ("0") bit, another 169 bits are skipped, and the 341st bit is tested for also being a zero ("0") bit. This search is repeated until either the entire block read into RAM has been successfully searched and tested, or a bit fails testing. In that case, the test is restarted for the next bit in RAM. For example, the second time around, the 2nd, 172nd, 342nd, etc. bits would be tested. This loop may have to be repeated up to 680 times before identifying the framing bits in the sequential input stream (the mean is 340 times).
The above know method has two major disadvantages: it is slow, and it requires upwards of 4760 bits of RAM. Neither of these disadvantages is fatal if implemented on a stand-alone chip with today's technology. However, both are of major concern if implemented on an integrated chip. The speed is especially critical given the high speed (45 Mhz) of the input stream.